Automated Organization of Caches Architecture
نویسنده
چکیده
We consider the case of a multi-discipline company distributed in several sites. These sites are linked with a sufficiently dimensioned Intranet which allows a good quality of service. We use caches to increase the comfort of the users for an external connectivity to Internet. These caches are organized so as to cooperate and so to optimize performances. The objective of this proposal is to use the principle of the learning process to direct automatically each user towards the most liable cache to contain his requested page. Furthermore, we describe, according to the same principle, an automatic organization method of cooperating caches architecture. In this context, it is more interesting to use several thematic self dedicated caches instead of a « big central» one. Each dedicated cache will correspond to a specific activity of the company.
منابع مشابه
Crosspoint Cache Architectures
We propose a new architecture for shared memory multiprocessors, the crosspoint cache architecture. This architecture consists of a crossbar interconnection network with a cache memory at each crosspoint switch. It assures cache coherence in hardware while avoiding the performance bottlenecks associated with previous hardware cache coherence solutions. We show this architecture is feasible for ...
متن کاملA Reusability-Aware Cache Memory Sharing Technique for High Performance CMPs with Private L2 Caches
For high-performance chip multiprocessors (CMPs) to achieve their maximum performance potential, an efficient support for memory hierarchy is important. Since off-chip accesses require a long latency, high-performance CMPs are typically based on multiple levels of on-chip cache memories. For example, most current CMPs support two levels of on-chip caches. While the L1 cache architecture of thes...
متن کاملA Power-Aware Multi-Level Cache Organization Effective for Multi-Core Embedded Systems
Recent system design trends suggest multicore architecture for all computing platforms including distributed and embedded systems running real-time applications. Multilevel caches in a multicore system pose serious challenges as cache requires huge amount of energy to be operated and cache increases unpredictability due to its dynamic behavior. Bandwidth and synchronization problems are also cr...
متن کاملReducing Sensitivity to NoC Latency in NUCA Caches
Non Uniform Cache Architectures (NUCA) are a novel design paradigm for large last-level on-chip caches which have been introduced to deliver low access latencies in wire-delay dominated environments. Typically, NUCA caches make use of a network-on-chip (NoC) to connect the different sub-banks and the cache controller. This work analyzes how different network parameters, namely hop latency and b...
متن کاملSegmented Addressing Solves the Virtual Cache Synonym Problem
If one is interested solely in processor speed, one must use virtually-indexed caches. The traditional purported weakness of virtual caches is their inability to support shared memory. Many implementations of shared memory are at odds with virtual caches—ASID aliasing and virtual-address aliasing (techniques used to provide shared memory) can cause false cache misses and/or give rise to data in...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1998